1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a decoupling capacitor formed in a semiconductor device, a semiconductor package including the decoupling capacitor, and a method of fabricating the semiconductor package.
2. Description of the Related Art
The integration of semiconductor packages mounted in electronic systems has increased in line with the integration of electronic systems. To obtain higher integration in the same area, semiconductor devices are perpendicularly stacked in addition to using a 2-dimensional plane mounting structure. Wire bonding has been generally used as a package assembling method and methods of perpendicularly stacking wafers on which semiconductor devices are formed, i.e., semiconductor chips, and electrically connecting the semiconductor devices to external power sources, etc, have been intensively researched.
FIG. 1 is a cross-sectional view of a conventional wafer stack package (WSP) having perpendicular vias. Referring to FIG. 1, in the conventional WSP or a chip stack package (CSP) having perpendicular vias, a wafer 20 is stacked on a printed circuit board (PCB) 10 using an adhesive 30. A semiconductor in the wafer 20 is electrically connected to an external source through perpendicular vias 40. In other words, the perpendicular vias 40 are connected to internal wires of the PCB 10 and conductive bumps 50 formed underneath the PCB 10, e.g., solder balls, and to a plurality of power sources, a plurality of signals, and a plurality of ground terminals of a system in which the conventional wafer stack package is mounted through the solder balls.
A method of forming the wafer stack package will now be described in brief. Pad parts or redistribution pad parts of the wafer 20 are perforated using a mechanical or chemical method to form via holes. Next, the via holes are filled with a conductive metal using a plating method or another method to form the perpendicular vias 40. The wafers 20, in which the perpendicular vias 40 are formed, are stacked with the adhesive 30 positioned between the wafers 20 using thermocompression or the like, and mounted on a PCB 10 or the like. Here, the coupling of perpendicular vias is achieved using conductive bumps. The adhesive 30 used for connecting the wafers 20 in the wafer stack package, however, remains as an unnecessary area in terms of electrical performance characteristics.
FIG. 2 is a plan view illustrating an arrangement structure of the vias 40 in the conventional wafer stack package of FIG. 1. Referring to FIG. 2, in a wafer stack package structure using the perpendicular vias 40, semiconductor devices in stacked semiconductor chips are generally connected to signals, power sources, and ground terminals. The semiconductor devices are connected to external power sources, external signal sources, and external grounds through perpendicular vias formed in outer ends of the semiconductor chips, e.g., power vias 42 for connections to the power sources, ground vias 44 for connections to the grounds, and signal vias 46 for connections to signals. Such vias may be formed in different shapes, different positions, or different arrangements. If necessary, different types of power vias may be distinguishably formed. If a plurality of signals are required, a plurality of signal vias may be formed so that the number of signal vias is equal to the number of signals.
Factors such as noise, signal delay, etc., affect a high speed operation of a semiconductor device in such a semiconductor package. In particular, when the number of signals simultaneously transmitted to a semiconductor device is high, such signals are coupled to parasitic inductance components of a board on which a semiconductor package is mounted and thus include noise. Such noise is generally referred to as power and ground noise.
As the operation speed of the semiconductor devices and the number of simultaneously transmitted signals has increased, the power and ground noise has also increased, which impedes the high speed operation of the semiconductor device. To address this problem, methods of designing power and ground paths to have lower inductances and adding a decoupling capacitor to a surface of a board, etc., to stabilize the power and ground voltages have been suggested.
In the latter method, a resistance and an inductance must be “0.” However, the effects of attempting to stabilize the power and the ground voltages by stabilizing the power and the ground voltages obtained by the decoupling capacitor are not very great due to a conductor path from a semiconductor device to the decoupling capacitor and internal equivalent series resistor (ESR) and equivalent series inductance (ESL) components of the decoupling capacitor.